1. Field of the Invention
The present invention relates to an input/output circuit suitable for use in a memory circuit for storing, for example, image data.
2. Description of the Prior Art
Conventionally, in a memory circuit of the described type, it has been the practice that input image data is written in a memory element after the transfer rate of the data has been converted to a lower frequency, and the data is read out of the memory element at the lower frequency and output after its transfer rate is converted to a higher frequency, and thereby, positive storage of the image data is ensured even if a memory element of a slower write and read speed is used (NIKKEI ELECTRONICS, 1985.3.11, pp. 219-239).
More particularly, referring to FIG. 3, reference numeral 1 denotes the whole of a memory circuit, and therein, each one-bit data of D.sub.G1 -D.sub.G8 constituting 8-bit image data D.sub.G is separately supplied to a serial/parallel conversion circuits 2A-2H, respectively.
As shown in FIG. 4, each of the serial/parallel conversion circuits 2A-2H is made up of D flip-flop circuits 3A to 3N of a master-slave type connected in series and adapted to acquire the data at the timing synchronized with a clock signal S.sub.CK of the image data D.sub.G and the data D.sub.G1 to D.sub.G8 are adapted to be supplied to the D flip-flop circuit 3A at one end.
Consequently, the data D.sub.G1 to D.sub.G8 are each sequentially transferred to the adjoining D flip-flop circuits, from the D flip-flop circuit 3A at one end toward the D flip-flop circuit 3N at the other end, at the timing synchronized with the clock signal S.sub.CK. By arranging the data to be entered into memory blocks 4A to 4H (FIG. 3) at intervals of predetermined periods of the clock signal S.sub.CK, it is possible to write the image data D.sub.G into the memory blocks 4A to 4H at a low frequency converted from the transfer rate of the image data D.sub.G at a high frequency.
Conversely, by reading out the data from the memory blocks 4A to 4H and outputting the same through the parallel/serial converters, it is possible to read out data at a low frequency and output the image data D.sub.G at a transfer rate converted to a high frequency.
There are problems with such input/output circuits using serial/parallel conversion circuits and parallel/serial conversion circuits that power consumption therein is large and a large instantaneous current is drawn thereby.
More particularly, in such master-slave type D flip-flop circuits formed of CMOS (complementary metal oxide semiconductor) devices, each circuit consumes tens of .mu.W/MHz/bit of power.
Further, in practice, when 30 MHz or so of image data is to be positively written into or read out from a memory element, 700 or so serially connected D flip-flop circuits become necessary for one bit of the image data.
Hence, 700 mW or so of power is totally consumed for one bit of the image data and this presents a problem of difficulty in arranging the circuit elements in the form of an integrated circuit.
Besides, in a D flip-flop circuit of the described type, 0.1 mA or so of instantaneous current flows for each circuit on the leading edge and the trailing edge of the clock signal S.sub.CK, and since the D flip-flop circuits constituting an input/output circuit in question operate in synchronism with the clock signal S.sub.CK, there has been a problem that a total of 70 mA or so of instantaneous current flows.
As a means to solve this problem, there is known a method to use a serial/parallel conversion circuit 5 as shown in FIG. 5 and FIG. 6.
That is, data D.sub.G1 to D.sub.G8 are passed through a selector circuit 7, whose contacts are switched over in synchronism with the clock signal S.sub.CK (FIG. 6(A)), and thereby supplied to two channels of serially connected D flip-flop circuits 8A to 8M and 9A to 9M.
The D flip-flop circuits 8A to 8M and 9A to 9M are adapted to transfer data D.sub.G1 -D.sub.G8 sequentially in synchronism with a clock signal S.sub.CK2 (FIG. 6(B)), whose frequency is that of the clock signal S.sub.CK divided by 2, and it is thereby possible to drive the D flip-flop circuits 8A to 8M and 9A to 9M at the low frequency and obtain data at this low frequency.
As a result, the consumed power can be reduced by 1/2 corresponding to the arrangement to use the clock signal S.sub.CK2 for the D flip-flop circuits 8A to 8M and 9A to 9M obtained by dividing the frequency of the clock signal S.sub.CK by 2.
Even if such an arrangement is used, the instantaneous current cannot be reduced and there still remains a practical difficulty in providing the circuit elements in the form of an integrated circuit.
Further, as shown in FIG. 7, the D flip-flop circuit of the described type is structured of transition gates 11 and 12 each thereof being formed of two CMOS transistors, inverting amplifiers 13, 14, and 15, each similarly formed of two CMOS transistors, and latch circuits 16 and 17 each formed of four CMOS transistors, and therefore, 18 transistors in all are used for the structure.
Hence, when 700 D flip-flop circuits are used for one bit as mentioned above, a total of a hundred thousand transistors will become necessary for processing 8-bit image data. When these are to be arranged on an integrated circuit, the area on one chip occupied by the D flip-flop circuits becomes larger, and this has involved a problem for the chip to become larger in size accordingly.